Hardware Implementation of Parallel Algorithm for Setting Up Benes Networks

Both Benes and Clos networks are rearrangeably non-blocking multi-stage interconnection networks. Benes network is a special case of Clos network which has inputs and outputs. The Benes network is constructed with switching nodes recursively. Due to their non-blocking property and relative smaller number of crosspoints, Benes/Clos networks have received much attention in both academia and industry. Benes/Clos networks have been used in many areas, such as interconnection network in parallel computers, multiprocessors system [1], and networks-on-chip [2][3][4][12][13]. In packet switching systems, the switch fabric must be able to provide internally conflict-free paths for the requesting packets in each time slot [5]. This is implemented by setting the states of all switches in the network. It is clear that the routing assignment (i.e., switch setting) scheme in Benes/Clos networks has a strong impact to the efficiency of the Bene/Clos networks. A number of switch setting algorithms have been developed in the past few decades, including sequential algorithms and parallel algorithms. Sequential algorithms such as looping algorithms [7] are designed for circuit switching systems where the switching configuration can be rearranged at relatively low speed. In [7], a switch setting algorithm with time complexity is proposed based on Waksman proof. As a matter of fact, using sequential algorithm, the N×N Benes network cannot be set up in less than time, because there are switches. The set-up time is much longer than the latency in Benes networks, which is for N×N network. In order to obtain a switch setting algorithm of complexity comparable to the network latency, parallel algorithms are needed. In [9], Nassimi and Sahni developed a parallel set-up algorithm which runs significantly faster than the sequential